Intellectual Property:
phyCore
Applications
Interface
Miscellaneous

 
 
Multi-port Programmable TDM Interface
Flexible serial interfacing and timeslot mapping of 1 to 16 ports  
 

UTOPIA L1 Slave
ATM Forum af-phy-0017.000 UTOPIA Level 1 v2.01
UTOPIA L2 Slave for phyCore
ATM Forum af-phy-0039.000 UTOPIA Level 2  
 
Multi-port Serial-UTOPIA Bridge

1-8 physical ports, ATM transmission convergence,
UTOPIA level 2 PHY interface

  

UTOPIA Interface Controller
Controls one or more UTOPIA interfaces
UTOPIA Scheduler
Controls flow control on a UTOPIA L2 interface to enforce
programmed cell rates
Telecom Bus Interface
Adds/drops timeslots on a synchronous bus
SDRAM Controller
Configures and controls synchronous DRAM
Generic Processor Interface
Address decode, handshaking, interrupt controller and interface
register set
 

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