phyCore comprises hardware and software that combines FPGA fabric resources, and one or more processors, into a powerful dataflow processor. phyCore performs the low-level tasks required to couple data flows to software processes. Since most of this functionality is implemented in hardware, the processor resources are freed for application processing, providing an order of magnitude performance boost over a pure software implementation.

phyCore works by coupling software operation to the data flow, through a hardwired queuing system. phyCore acts as a hardware real-time operating system, managing tasks which are triggered by external events at the traffic interfaces. The architecture accounts for variation in processing time and irregular arrival of data. Communication between hardware and software is provided at zero latency. These features combine to produce a flexible hardware/software datapath that is free from the performance bottleneck of conventional bus-based systems.

phyCore can be deployed in a number of configurations, allowing trade-offs of performance, cost and integration. The choice of processor is the main factor:

phyCore is delivered as a hardware netlist and compiled C library. Along with example code, this provides a solid foundation for new system designs characterised by -

• High performance
  • optimal hardware/software partitioning and glue-less interfaces
• Low cost
  • rapid deployment and reduced bill of materials
• Low development risk
  • accurate modelling and transparent design process
• Ultimate scalability
  • Vertical integration - scale up without overloading the control infrastructure
  • Greater integration - lower system interconnect complexity